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Cadence IP makes Dream Chip’s AI vision come true

AI chip design doesn’t have to be complex! With Cadence’s ready-to-go IP and comprehensive toolsets, you’ll be developing the application before the chips have even left their wafers.

In ipXchange’s second discussion from Cadence’s booth at Embedded World 2024, Guy chats with Markus from Dream Chip, and Robert from Cadence, about how 3D car detection for ADAS is possible using a 2D camera and some great machine learning DSP. This is accompanied by a beautiful live demo.

As Markus explains, Dream Chip’s latest automotive SoC is taking in the live image of some model cars, inferring several key points of interest on these objects, and creating a 3D bounding box that surrounds a vehicle so that it can be viewed as a 3D object. This is running on Linux, but the setup can also be implemented on real-time operating systems.

Cadence’s NNA 110 AI accelerator IP is key to this inferencing capability, as well as Cadence’s Tensilica AI DSP for object detection. In conjunction with its own IP, Dream Chip’s SoC is capable of 10 TOPS of optimised AI performance.

Guy then asks Robert how Cadence’s digital AI processing IP helps designers – both of chips and end products – implement AI in this brave new world. Robert responds with how specialised tooling is key to this, such as the digital design flow RTL to GDS tool that enables manufacturers to use GlobalFoundries 22 nm process.

From an AI training perspective, tooling like Cadence’s XNNC compiler enables neural network mapping to the hardware, and these models can be trained in popular frameworks like PyTorch.

Cadence’s Helium Virtual Studio also enables manufacturers like Dream Chip to build a virtual twin of the hardware due to be manufactured so that they can start on the software development long before the chips are ready. This saves lots of time during development!

Cadence provides so much more than simply great IP for putting into chips. The tools that you need to develop chips for use in automotive AI vision applications like Dream Chip’s demo, for example, are readily available so that your overall product development can be well ahead of your manufacturing runs.

This means that when you say you’ll have a product ready for market by a certain date, you’ll know that it works, and that it works well!

If you’re a chip designer and you wish to work with Cadence on a new AI SoC build, check out our board page for the Tensilica Vision DSP for glimpse of what this innovative company can offer. Fill out the form, and ipXchange will connect you with Cadence for an introduction.

Keep designing!

Enjoyed this discussion? Check out our previous IP-related interviews from Embedded World 2023 and 2024:

Cadence DSP provides LLM and LVM AI at the edge

An expertly crafted 64-bit RISC-V core in an affordable single-board computer for industrial IoT

Cadence Tensilica Vision DSP For Energy-Efficient On-Device AI

Looking for a streamlined way to add AI functionality to your next chipset?

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