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In the Quadric Chimera GPNPU
The Quadric Chimera GPNPU is a hybrid processor IP platform that combines the flexibility of general-purpose C++ programmability with high-performance AI inference. Designed to replace fixed-function NPUs and fragmented SoC architectures, Chimera enables developers to write both AI models and control logic in a unified programming model, eliminating the need for separate accelerators, CPUs, and DSPs.
At the heart of the Quadric Chimera GPNPU is a scalable architecture built around single-core IP blocks that can be clustered for performance targets ranging from 7 TOPS to 864 TOPS. Each Chimera core includes tightly coupled scalar units, vector tensor engines, and systolic arrays, enabling seamless transitions between traditional compute and neural workloads without task switching or external coordination.
By unifying neural graph execution and real-time C++ code into a single instruction stream, the Quadric Chimera GPNPU offers a streamlined development process and significant silicon savings. Developers can extend functionality by writing custom operators in C++, compiled to run at full speed within the graph—future-proofing applications against evolving AI models without requiring new hardware.
Safety-critical and high-performance designs are well supported. The Quadric Chimera GPNPU QC-M Series includes automotive-grade versions with ISO 26262 ASIL support, making them ideal for ADAS and autonomous vehicle SoCs. Quadric also supports rich development tools including their Compute Library (CCL), compiler SDK, and integrated simulation environments.
With pre-silicon IP licensing options, the Chimera platform scales from ultra-low-power single-core inference engines to dense compute clusters targeting edge servers and ADAS domain controllers. The Quadric Chimera GPNPU has already been adopted by DENSO for automotive applications and was awarded “Best Edge AI Processor IP” by the Edge AI & Vision Alliance in 2025.
Register your interest
In the Quadric Chimera GPNPU